Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch
Yoshiyuki Nakamura · IEICE Transactions on Information and Systems · 2006
In this paper, we provide a practical formulation of the problem of identifying all error occurrences and all failed scan cells in at-speed scan based BIST environment. We propose a method that can be used to identify every error when the circuit test frequency is higher than the tester frequency. Our approach requires very little extra hardware for diagnosis and the test application time required to identify errors is a linear function of the frequency ratio between the CUT and the tester.