A low-power variable-length FFT processor base on Radix-24 algorithm
Qingwang Lu, Xin’an Wang, JiuChong Niu · 2009
A low-power variable-length FFT processor is proposed in this paper. Mixed-radix algorithm and Radix-24single path delay feedback (SDF) pipeline architecture are chosen to achieve low computation complexity and high reconfigurable flexibility. The system can be reconfigured as 16, 32, 64, 128, 256, 512, 1024, 2048 or 4096-points FFT. The FFT processor is implemented with SMIC 0.18 ¿m CMOS technology. The core area is 4 mm2. Compared with other design, the proposed FFT processor consumes lower power and smaller area due to adopting high radix algorithm.