A three dimensional systolic array architecture for fast matrix multiplication
Richard Linderman, Walter H. Ku · 2005
In recent years one and two dimensional systolic arrays have been designed to implement a wide range of matrix operations and signal processing algorithms. This paper proposes a three dimensional systolic array architecture of N3processors to further extend the performance advantages which can be achieved through regular local data transfer. The three dimensional array is discussed in the context of fixed point matrix-matrix multiplication which requires O(N3) multiplications and additions. The array pipelines N of these problems to attain a throughput rate which is practically independent of N. The performance, size, and fault tolerance of the array are discussed for the case N=32.