A High-Speed Low-Power Rail-to-Rail Buffer Amplifier for LCD Application
Chih‐Wen Lu, Peter H. Xiao · 2006
A high-speed low-power rail-to-rail class-B buffer amplifier, which is suitable for liquid crystal display applications, is proposed. The summing circuit is biased by the constant current sources to applicable different supply voltages. The buffer draws little current while static but has a large driving capability while transient. The circuit achieves the large driving capability by employing simple comparators to sense the transients of the input to turn on the output stages, which are statically off in the stable state. This increases the speed of the circuit without increasing static power consumption too much. An experimental prototype output buffer implemented in a 0.35-mum CMOS technology demonstrates that the circuit can operate under a wide power supply range. Quiescent currents of 5.4 muA and 7.4 muA are measured for power supplies of 3.3 V and 8 V, respectively. The buffer exhibits the settling time of 1.5 mus for a voltage swing of 0.1~(VDD$0.1) V under a 600 pF capacitance load. The area of this buffer is 29.3times86.3 mum2