MoCReS: an Area-Efficient Multi-Clock On-Chip Network for Reconfigurable Systems
Arun Janarthanan, Vijay Swaminathan, Karen A. Tomko · 2007
Design of a high performance, flexible on-FPGA communication architecture with minimum area overhead presents a great challenge. In this research, we implement a minimum area and high performance packet-switched router for FPGA based NoCs. Our 5-port virtual cut-through router has an area overhead of only 282 Virtex-4 slices (a marginal 0.57% of XC4VLX100) and operates at 357 MHz supporting a competitive data rate of 2.85 Gbit/s. We gain in router area and performance by reducing the logic depth of the central arbiter and cross point matrix. Further, we utilize our router to construct a mesh based multi-clock on-FPGA NoC. We enable the routers to function at independent operating frequencies, dictated by placement and routing constraints in FPGA. We demonstrate the functionality and characterize the router for area and performance.