Analysis of a fault-tolerant ATM switch based on a parallel architecture
S. Segkhoonthod · 1995
This paper presents a fault-tolerant ATM switch which adapts the idea of using MINs in parallel. It has a distribution network to distribute incoming packets to several routing networks arranged in parallel. Consequently, the IPC is simply required to submit packets to the distribution network. As the latter is designed to perform some of the routing itself, the routing networks are not required to carry out the whole routing process; consequently incomplete (i.e. truncated) routing networks are used. As a result, the overall complexity of the switch is not further increased by the introduction of the distribution network. The distribution network is also in charge of re-routing packets in the presence of a fault. Unlike other fault-tolerant networks where the routing algorithm is usually modified in order to avoid faults, in the proposed switch there is no modification to the routing algorithm in fault conditions: hence the re-routing process is simple and the complexity of switching elements is kept low. Further, it will be shown that the proposed switch gives both improved performance and lower complexity than replicated MINs. 1