On crosstalk fault detection in hierarchical VLSI logic circuits
A. Liaud, Jean Yves Fourniols, Étienne Sicard · 2002
A realistic crosstalk fault detector operating at hierarchical layout and logic level is presented. A set of filtering schemes are proposed to reduce considerably the set of probable single and multiple coupling faults with details on substrate resistivity and unbalanced buffer implications. Comparisons between flat and hierarchical layout approaches are reported together with the performances of the tool for various IC implementations.>