Module recognition and its application to LVS of ASIC
Shi Lin-chu · 2002
LVS (Layout Versus Schematic) is an important procedure in ASIC design. LVS includes 2 steps: extraction of devices and net-lists from layout with an EDA system to form the schematic, the so-called "extracted schematic", and identification and verification of the extracted schematic with another schematic designed independently upon layout. The former is more important than the latter. Module recognition plays a very effective role during extraction of schematic from layout. The theoretical principle is described in the paper, followed by a detailed description of an actual method, with some examples of bipolar analog ASIC design.