A 1.2 V built-in architecture for high frequency on-line Iddq/delta Iddq test
S. Dragic, Martin Margala · 2003
A novel low-voltage design of Iddq/delta Iddq architecture suitable for a Built-In-Self-Test (BIST) implementation with analog, digital or mixed-signal cores is proposed. In testing mode, the architecture performs a non-functional Iddq and delta Iddq test which enables a more accurate fail/pass decision. A 1.2 V high-frequency current amplifying cell is developed as a central part of the Iddq/delta Iddq current monitor. With a sensitivity of less than 200 nA, the monitor achieves a gain-bandwidth product of 6.8 GHz, a low frequency current gain of 48 dB, and a high linearity for input current range (-15 /spl mu/A, 15 /spl mu/A). Its functionality and high performances are verified in experimental simulations. The Iddq fault detector has been implemented in a 0.13 /spl mu/m CMOS technology with 1.2 V power supply.