Efficient Assertion Based Verification using TLM
Ahmad Rizky Nusantara Habibi, Sofiène Tahar, Amer Samarah, Dong-Lin Li, Otmane Aı̈t Mohamed · 2006
Recent advancement in hardware design urge during a transaction based model as a new intermediate design level. Supporters for the Transaction Level Modeling (TLM) trend claim its efficiency in terms of rapid prototyping and fast simulation incomparison to the classical RTL-based approach. Intuitively, from a verification point of view, faster simulation induces better coverage results. This is driven by two factors: coverage measurement and simulation guidance. In this paper, we propose to use an abstract model of the design, written in the Abstract State Machines Language(AsmL), in order to provide an adequate way for measuring the functional coverage. Then, we use this metric indefining the fitness function of a genetic algorithm proposed to improve the simulation efficiency. Finally, we compare our coverage and simulation results to:(1) random simulation at TLM; and (2) the Specman tool of Verisityat RTL.