Simulating fixed point systems
J.P. Thorlby, Alister Graham Burr · 1993
This paper describes a technique which can be used for simulating fixed point arithmetic using 'standard' SPW rather than the hardware design system (HDS). The method is relatively quick in system development and does not require the purchase of HDS. The drawback is that the extra features of HDS are not present, such as VHDL generation. The technique is specifically developed for the Q15 format as used in the Texas Instruments TMS320C25 DSP chip. It is illustrated by simulation of a fixed point FFT algorithm.