Ultrafast compact CMOS dividers
J.-P. Theis, H. Schlimper · 2002
This paper introduces a new class of ultrafast and compact divider circuits. They are obtained by a systematic parallelization of a simple restoring division algorithm. Emphasis is put onto the stepwise parallelization methodology. Furthermore, a detailed discussion of implementational aspects is presented, including timing and layout. When, compared to SRT-schemes, these divider circuits allow a speed-up by a factor 2 to 3, while the cost is nearly identical. In particular, it is expected that double-precision IEEE Std. 756 floating-point division is performed within ca. 13 ns in 0.3 /spl mu/m, CMOS technology.