Design space exploration for real-time embedded stream processors
Sridhar Rajagopal, Joseph R. Cavallaro, Scott Rixner · IEEE Micro · 2004
We explore tradeoffs between organization and number of ALUs and clock frequency in a stream processor. The tool provides candidate low-power configurations and estimates of their real-time performance. The tool relates instruction-level, subword, and data parallelism to functional units' organization and utilization. The exploration methodology is applicable to all embedded-processor designs in signal and media processing.