Instruction scheduling and executable editing
Eric C. Schnarr, James R. Larus · 1996
Modern microprocessors offer more instruction-level parallelism than most programs and compilers can currently exploit. The resulting disparity between a machine's peak and actual performance, while frustrating for computer architects and chip manufacturers, opens the exciting possibility of low-cost instrumentation for measurement, simulation, or emulation. Instrumentation code that executes in previously unused processor cycles is effectively hidden. On two superscalar SPARC processors, a simple, local scheduler hid an average of 13% of the overhead cost of profiling instrumentation in the SPECINT benchmarks and an average of 33% of the profiling cost in the SPECFP benchmarks. 1. Introduction Modern microprocessors offer more instruction-level parallelism than most programs and compilers can currently exploit. For example, the most recent generation of RISC chips---the Digital Alpha 21164, IBM/Motorola Power PC 620, SGI R10000, and Sun UltraSPARC---are 4way superscalar processors th...