An ultra-low energy asynchronous processor for Wireless Sensor Networks
Luca Necchi, Luciano Lavagno, Davide Pandini, Laura Vanzago · 2006
This paper describes the design flow used for an asynchronous 8-bit processor implementing the Atmel AVR instruction set architecture. The goal is to show dramatic reductions in power and energy with respect to the synchronous case, while retaining essentially a traditional design flow. The processor was implemented in a 130nm technology using desynchronization, starting from an initial design downloaded from OpenCores.org. It consumes 14 pJ per instruction to deliver 170 MIPS at 1.2 V, and 2.7 pJ per instruction to deliver 48 MIPS at 0.54 V. It thus dramatically improves the energy consumed per instruction with respect to previous results from the literature