A programmable 32 tap digital interpolation filter in 1.5 mu m CMOS with 80 MHz output data rate
W. Haberecht, E. DeMan, Michael H. Schulz · 2002
A 32 tap programmable, digital FIR filter for pulse shaping is presented. The filter performs interpolation of the input data sampled at a maximum clock frequency of 40 MHz. The output data rate is 80 MHz. The data inputs and outputs are emitter-coupled-logic (ECL)-compatible. The stepped coefficient set contains 256 coefficient bits, which can be serially loaded. To reduce the effect of power bus switching noise (due to the large clock system capacitance) a special clock system with distributed clock subsystems is used. With a sequence of 3500 deterministic test vectors a 98% stuck-at fault coverage can be achieved. The chip contains 159.022 transistors on a total area of 78 mm/sup 2/ and has been realized in 1.5 mu m CMOS technology.>