A parallel-pipelined processor for fast fourier transform
Tze‐Yun Sung, C. F. Chen · Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits · 2004
In this paper, we proposed a novel VLSI FFT processor based on parallel-pipelined constant geometry algorithm (PCGA). This processor provides constant geometry for each stage of FFT, data reordering is not needed any more. Especially, the PCGA FFT processor increases throughput with increasing number of input points, and sufficiently exploits the advantage of parallel-pipelines computation for digital signal processing applications.