Architecture for MPEG2 MP@HL real time motion estimator
Takao Onoye, Gen Fujita, Isao Shirakawa, K. Matsumura, H. Ariyoshi, S. Tsukiyama · 2002
A VLSI architecture of a motion estimator is proposed, dedicated to MPEG2 MP@HL, which adopts a two-level hierarchical searching algorithm in detecting motion vectors. A novel mechanism is introduced into the full-search procedure which attempts the maximum possible reuse of reference pixels to reduce the bandwidth of frame memory interface. The proposed architecture has been integrated into a 0.6 /spl mu/m triple-metal CMOS chip which contains 1200 K transistors on a 12.2/spl times/12.7 mm/sup 2/ die. The input clock rate can be attained up to 133 MHz, which enables the real time motion estimation for MPEG2 MP@HL.