Parallelization of DVFS-enabled H.264/AVC Decoder on Heterogeneous Multi-core Platform
Yu-Sheng Lu, Chin‐Feng Lai, Yueh‐Min Huang · 2012
Using a multi-core system to process real-time data of high computational complexity has become a popular solution for effectively enhancing system processing efficiency. However, the high-power consumption of a multi-core system remains a problem, particularly to handheld devices. Applying DVFS to properly decrease the system voltage and frequency can effectively save system power loss, nevertheless, the question of how to effectively and accurately configure a dynamic DVFS system to avoid missing a deadline or extra power loss remains to be widely discussed. This study examines many previous parallel processing architectures and DVFS mechanisms, and proposes two different orientations of parallel DVFS-enabled H.264/AVC decoders, and implements a multimedia heterogeneous multi-core platform. Based on experimental data, the impact of two parallel DVFS-able processing systems on H.264 decoding performance and power loss are studied.