Test strategies for a 3-D stack multichip module space flight computer
K. Sasidhar, L. Alkalai, A. Chatterjee · 2002
Advanced packaging technologies such as 3D chip stacking, Multichip Modules (MCMs), and 3D stacks of MCMs provide an opportunity for significant reduction in system mass, volume and power. Unfortunately, it also poses some major testing challenges that need to be resolved before it becomes a widely adopted solution. Among the most challenging problems are achieving acceptable assembly yields and meeting product quality requirements. Both these problems can be significantly reduced by adopting testing approaches which guarantee the integrity and performance of the 3D stack of MCMs. In this paper, we present test strategies for the 3D stack of MCMs used by the flight computer of the New Millenium Program (NMP) Deep Space-1 spacecraft, to be launched in July 1998. The proposed strategies are based on the IEEE 1149.1. Boundary Scan Standard architecture. Test chips are incorporated in some of the approaches for reliable test and diagnosis of a 3D MCM stack. Further, all the test strategies are compared and ranked with respect to test time, test hardware, number of test lines, and test reliability.