A staged carry-save-adder array for Montgomery modular multiplication
Jhing-Fa Wang, Po‐Chuan Lin, Ping-Kun Chiu · 2003
In this paper, an efficient VLSI architecture to compute the n-bit Montgomery modular multiplication is proposed. By using the staged carry save adder (CSA) array, the computation cycles of addition reduced by about 3n/8. In addition, we apply the switch unit to save 2Q-2 registers from the traditional Q-bit CSA. Compare with the original method, the total clock cycles can be reduced by 68% in the case of n=1024 and Q=512 bits.