Design of a memory-scalable wavelet-based image codec
Yiliang Bao, Houng-Jyh M. Wang, C.‐C. Jay Kuo, Randall M. Chung · 2002
The goal of this research is to develop a high performance image codec to be implemented in a digital signal processor (DSP). This DSP chip has only a small amount of internal memory that is fast enough to keep up with the clock cycle of CPU. A new wavelet image codec called the scalable binary description (S-BiD) codec is proposed to achieve this goal. S-BiD, consists of an external wavelet transform and the block-based quantization scheme. The external wavelet algorithm uses a DWT-specific pre-fetching technique to reduce the impact of large access delay of a bulk storage device. Wavelet coefficients are quantized into a set of interleaved multiple bit-streams that describe the three layers in the quantization hierarchy, i.e. blocks, subbands and coefficients, respectively. The codec can generate good compressed images even when the size of the cache memory is less than 4 Kbyte. With a cache memory of 16 Kbyte, its PSNR performance is comparable with all other codecs while its coding time is the shortest. If more resources are available, its performance will be even better.