Review of 3-D network-on-chip topologies
Shivam Tyagi, Shweta Bohare · 2011
The demand for faster processors having high processing capability over area ratio is increasing. The topologies play a major role in the area and network latency. In this paper, we have investigated scope for extending 2-D topologies for 3D network-on-topologies. Most recently, chips with 64 or more processors have already been developed in 2D-networks [7, 9]. In this paper, we discuss many more effective 3-D NoC designs and their architecture.