Logic synthesis of synchronous parallel controllers
James Pardey, Martin Bolton · 2002
The contribution of this work is a VHDL methodology for the design of synchronous parallel controllers that supports RTL representation and verification, state assignment and decomposition, logic synthesis, and gate-level consistency checking. A simple extension to FSM techniques, based on Petri nets, is used to represent concurrency and check for parallel synchronization errors; the concept of synchronous-safeness is introduced to enable maximum latching of data path units. A synthesizable VHDL template is described in which ASSERTION statements are used to enable the syntactic and semantic correctness of the model to be tested in unison. The method yields more efficient implementations than FSM designs when concurrency forms part of the specification, and in a practical design, a 50% area reduction and 40% speed improvement over the best FSM synthesis were achieved.>