Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing
Ho Fai Ko, Nicola Nicolici · 2005
This paper introduces a new method to construct functional scan chains at the register-transfer level aimed at increasing the delay fault coverage when using the skewed-load test application strategy. It is shown how by consciously creating scan paths prior to logic synthesis, both the transition delay fault coverage and circuit speed can be improved.