Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip
Daniele Ludovici, Georgi Gaydadjiev, Davide Bertozzi, Luca Benini · 2009
In the context of nanoscale networks-on-chip (NoCs), each link implementation solution is not just a specific synthesis optimization technique with local performance and power implications, but gives rise to a well-differentiated point in the architecture design space. This in an effect of the tight interaction existing between architecture and physical design layers in nanoscale technologies.