A pipelined memory management algorithm for distributed shared memory switches
X. Li, I. Elhanany · 2005
The distributed shared memory (DSM) packet switching architecture has attracted much attention recently, predominantly due to its ability to overcome the inherent memory-bandwidth limitation of output-queued switches. Its performance has been studied from a theoretical point of view by exploring the conditions under which it can emulate an output-queued switch. At the core of the DSM design is a memory management algorithm that determines the memory units to which arriving packets are forwarded. However, the complexity of such algorithms found to date is O(N), where N denotes the number of ports in the system, thereby inherently limiting the scalability of the scheme. In this paper, we propose a novel pipelined memory management algorithm for DSM switches which offers reduced timing complexity at the cost of fixed latency. Moreover, we demonstrate how processing and memory-access speedup factors yield a highly scalable DSM switch architecture design.