Hardware realization of a Hamming neural network with on-chip learning
Alexandre Schmid, Yusuf Leblebici, D. Mlynek · 2002
This paper addresses the mixed analog-digital hardware implementation of a Hamming artificial neural network with on-chip learning. The developed integrated circuit architecture consists of a charge-based variable-weight neural network, and a digital module implementing the chip control, as well as the on-chip learning algorithm as a hardware-oriented adaptation of the well-known error-correction algorithm. Both the analog and the digital parts interact with each other to perform a pattern recognition task. A dedicated digital memory unit acts as the interface to temporarily hold the newly processed weights. We describe the actual realization as well as the design-flow which led to this development, including C software simulation, full-custom design and automated VHDL-based synthesis.