Power variance analysis breaks a masked ASIC implementation of AES
Yang Li, Kazuo Sakiyama, Lejla Batina, Daisuke Nakatsu, Kazuo Ohta · 2010
Abstract—To obtain a better trade-off between cost and se-curity, practical DPA countermeasures are not likely to deploy full masking that uses one distinct mask bit for each signal. A common approach is to use the same mask on several instances of an algorithm. This paper proposes a novel power analysis method called Power Variance Analysis (PVA) to reveal the danger of such implementations. PVA uses the fact that the side-channel leakage of parallel circuits has a big variance when they are given the same but random inputs. This paper introduces the basic principle of PVA and a series of PVA experiments including a successful PVA attack against a prototype RSL-AES implemented on SASEBO-R.