A system for efficiently self-reconstructing E-1 1/2 track switch torus arrays
Tadayoshi Horita, Itsuo Takanami · 2002
A mesh-connected processor array consists of many similar processing elements (PEs), which can be executed in both parallel and pipeline processing. For the implementation of an array of large numbers of processors, it is necessary to consider some fault tolerant issues to enhance the (fabrication-time) yield and the (run-time) reliability. We introduce the E-1 1/2 -TS torus array ray model and apply the EAR method (that is an extended approximate reconfiguration method) to the array. We show that the E-1 1/2 -TS torus arrays with the hardware realization of the EAR algorithm are very efficient at the point of the array yield (or reliability) and suitable for run-time as well as fabrication-time fault-tolerance for mesh or torus connected processor arrays even though an additional logic circuit (about 200 gates per processor) is required.