Studies in VLSI technology economics. IV. Models for gate array design productivity
C.F. Fey, D. Paraskevopoulos · IEEE Journal of Solid-State Circuits · 1989
An empirical model of design productivity is presented and its implications for current and future design are discussed. Model and observed values correlate well (the correlation coefficient is 0.85). The analysis encompasses 70 designs, primarily gate arrays, of up to 25000 gates from five major corporations, designed during 1983-8. The estimate of design productivity enables the determination of normalized productivity, manpower, and schedule. The normalized design productivity adjusts for differences in the design tasks, permitting standardized productivity measurements for planning and for benchmarking.>