Design and Verification of VLSI Based AES Crypto Core Processor Using Verilog HDL
N. Deepthi Priya · 2013
Advanced Encryption Standard (AES), has received significant interest over the past decade due to its performance and security level. In most of the prev ious works subbytes and inverse subbytes are implemented in Separate Modules using lookup table method. In this paper we used combinational logic which helps for making inner round pipelining in an efficient manner. Furt hermore, composite field arithmetic helped in obtai ning lesser area. Using proposed architecture, a fully sub pipe lined encryptor/ decryptor with 3 substage pipelini ng in each round can achieve a throughput of 25.89Gbps on Xilinx xc5vlx110t-1 device which is faster. This AES design was implemented using Verilog HDL and synthesized with Xilinx ISE using Spartran3 Xilinx Family , Simulation and Verification was don e using Mentor-Graphics ModelSim-6.5e and achieved the maximum through put..