An efficient two-dimensional pipeline architecture for digital signal processing operation
Parijat Mukherjee · Third Annual IEEE Proceedings on ASIC Seminar and Exhibit · 2002
An efficient two-dimensional pipelined systolic architecture which can perform convolution operations in 2n+b/2 time units as opposed to O(bn) time needed for the sequential algorithm on a single processor is discussed. A very efficient pipelined multiplier, which enjoys all the merits of a systolic scheme and can be made a part of an ASIC library of medium-scale integration (MSI) cells, is also briefly discussed.>