A Novel Method to Improve the Test Efficiency of VLSI Tests
Hailong Cui, Sharad C. Seth, Surabhi Mehra · Lincoln (University of Nebraska) · 2002
This paper considers reducing the cost of test appli-cation by permuting test vectors to improve their defect coverage. Algorithms for test reordering are developed with the goal of minimizing the test cost. Best and worst case bounds are established for the performance of a reordered sequence compared to the original se-quence of test application. SEMATECH test data and simulation results are used throughout to illustrate the ideas. 1