A load-balanced switch with an arbitrary number of linecards
Isaac Keslassy, Shang-Tse Chuang, Nick McKeown · 2004
The load-balanced switch architecture is a predicting way to scale router capacity. It requires no centralized scheduler, requires no memory operating faster than the line-rate which can be built using a fixed, optical mesh. In a recent paper it is explained how to prevent packet missequencing and provide 100% throughput for all traffic patterns, and described the design of 100 Tb/s router using technology available within three year there is one major problem with the load-balanced switching makes the basic mesh architecture impractical: Because the optical mesh must be uniform, the switch does not work when one or more linecards is missing or has failed. Instead we can use the passive optical switch architecture with MEMS switches the reconfigured only when linecards are added and deleted, all the router to function when any subset of linecards is presently working. In this paper we derive an expression for the number of MEMS switches that are needed, and describe an algorithm to configure them. We prove that the algorithm will be a always correct configuration in polynomial time, and show example of its running time