Techniques for minimizing power dissipation in scan and combinational circuits during test application
Vinay Dabholkar, S. Chakravarty, Irith Pomeranz, Sudhakar M. Reddy · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1998
Reduction of power dissipation during test application is studied for scan designs and for combinational circuits tested using built-in self-test (BIST). The problems are shown to be intractable. Heuristics to solve these problems are discussed. We show that heuristics with good performance bounds can be derived for combinational circuits tested using BIST. Experimental results show that considerable reduction in power dissipation can be obtained using the proposed techniques.