Memory synthesis for high speed DSP applications
P.E.R. Lippens, Jef L. van Meerbergen, A. van der Werf, Wim Verhaegh, Brian McSweeney · 2002
Describes technique for performing automatic memory allocation and address allocation for high-speed applications. Memory access conflicts are solved and a global strategy to merge memory units is presented. Efficient reuse of memory locations is obtained by the proposed address allocation techniques. The techniques are based on a stream model for describing data transport. As a specific application, the memory management of the PHIDEO silicon compiler is discussed.>