Built-in self parallel testing for functional faults in megabit RAMs
Young Do Hur, H.M. Cho, J.H. Lee, S.B. Cho · 1991
A test algorithm and design scheme are proposed for a built-in self testing technique for functional faults in semiconductor random access memories. The test algorithm detects stuck-at and pattern sensitive faults over a neighborhood of nine cells. An n-bit memory is composed of p square sub-arrays, and this algorithm takes 2310 (n/p)/sup 1/2/ testing cycles. The row address generator, test pattern generator, parallel pattern loader, and parallel data comparator are added to the conventional RAM circuits for the built-in self testing function.>