Hierarchical test pattern generation: a cost model and implementation
H.B. Min, H.-t.A. Luh, William A. Rogers · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1993
A cost model for and implementation of a hierarchical test generation technique are presented. The cost model is based on fundamental test generation activities such as implication, justification, and backtracking. The model shows that the cost of hierarchical test generation grows as G log G under some realistic assumptions, while the cost of gate-level test generation may grow as fast as G/sup 2/, where G is the number of gates in a circuit under test. This implies that hierarchical test generators should be much faster than flat test generators on large circuits. The implementation of the hierarchical test generation is fan-out-oriented and uses a minimal hierarchical representation of the circuit and functional level heuristics to perform implication, propagation, and backtracing with high-level functional models. Experiments with three hierarchically described circuits show that hierarchical test generation is 1.5 to 8.9 faster than flat gate-level generation.>