Implementation of the 65nm Cell Broadband Engine
M. Riley, Brian Flachs, S.H. Dhong, Gilles Gervais, S. Weitzel, Mingjun Wang, David Boerstler, M. Bolliger, J. Keaty, J. Pille, Robert F. Berry, Osamu Takahashi, Y. Nishino, Taku Uchino · 2007
The first generation cell broadband engine processor introduced the cell architecture that consists of nine processor cores fabricated in the 90 nm CMOS SOI technology. This paper describes the advances made by moving the cell broadband engine design from 90 nm CMOS SOI to 65 nm CMOS SOI.