Integrated parallel scrambler design for high-speed transmission systems
S.H. Lee, P.J. Lee · 2003
A general parallel scrambling procedure based on exact relationships between high-speed and low-speed m-sequences is described. In particular, a novel implementation scheme using only one pure-cycling shift register without any exclusive-OR (XOR) gate in the feedback loop for generating the parallel scrambling sequences is presented. The use of a crosspoint switch in this method makes it applicable to a selectable multiplexing factor, thereby enabling the design of a general-purpose parallel scrambling circuit.>