Neural networks simulation with array processors
Francesco Pazienti · 2002
A strategy is presented for implementing neural models, based on an array of interconnected processing elements. A proprietary VLSI parallel processing chip (the array chip ACIIM) is briefly described. It incorporates 16 16-bit processors, 8 kBytes of local memory, external logic, and interface hardware in a single package. Using this chip, a 128-processor computer has been built, the array processor APx, which fits on two circuit boards and plugs into the backplane of an IBM PC AT microcomputer. By providing peak rates of up to 1600 32-bit MIPS and 160 MFLOPS, the APx accelerator achieves as much as a thousandfold improvement over PC/workstations for many computationally intensive tasks.>