An array architecture for fast computation of discrete Hartley transform
Anindya Sundar Dhar, Swapna Banerjee · IEEE Transactions on Circuits and Systems · 1991
Fast computation of the discrete Hartley transform (DHT) may be performed by employing a set of linear arrays of Givens rotors. It is shown that the interconnections between the linear arrays can be realized in a regular fashion governed by a permutation cycle that can be determined by simple arithmetic involving a primitive root of the transform length. A suitable implementation of the Givens rotor with add/subtract units and hard-wired shifters is also suggested.>