Parallel ultra large scale engine SIMD architecture for real-time digital signal processing applications
P. Marriott, Ivan C. Kraljic, Yvon Savaria · 2002
The instruction set and architecture of a SIMD processor optimized for real-time digital signal processing applications is presented. A novel structure allows computation and data I/O to be performed in parallel, provides interprocessor communications and enables the cascade of multiple chips without glue-logic to provide systems with large numbers of processors. Powerful processing elements and instruction set architecture allow complex real-time linear and non-linear algorithms to be coded. Dynamically reconfigurable systems can be also be built. A demonstrator chip was manufactured by ChipExpress. Benchmark comparisons and the methodology used to implement image processing applications on the PULSE, are also presented.