Configuration of a boundary scan chain for optimal testing of clusters of non boundary scan devices
Yoon-Hwa Choi, T. Jung · International Conference on Computer Aided Design · 1992
Testing of boards containing a mixture of boundary scan components and clusters of non-boundary scan devices is an interesting problem. If a tester cannot contact the non-scan circuitry, the inputs and outputs of onboard boundary scan devices may be used as virtual tester pins. In this case, the time for testing the cliuters depeds on how the boundary scan chips are connected into a longer scan chain. This paper presents a technique for configuring a chain of boundary scan chips to minimize the test time for cliuters.