Path delay ATPG for standard scan design
H.C. Wittmann, M. Henftling · European Design Automation Conference · 1995
Path delay fault test generation for standard scan design is topic of this work. A twenty-valued and a nine-valued logic are presented that are best-suited for the generation of robust and nonrobust tests. The scan design is used in two different ways: functional justification and scan shifting. Excellent experimental results considering all functional paths of benchmark circuits demonstrate the effectiveness of our approach.