The design of a testable parallel multiplier
S.J. Hong · IEEE Transactions on Computers · 1990
A scheme for an easily testable multiplier and the corresponding test generation procedures are presented. To provide 100% controllability of the summand-counter, the summand-generator is modified. The modified summand-generator can be implemented with little hardware overhead. Since the summands are 100% controllable, the summand-counter can be constructed with the minimum number of adder cells. The multiplier is not C-testable, but can be tested with a small numbers of test vectors, i.e. 3n+60 vectors. It requires only one extra input, whereas C-testable multipliers usually require at least four or five extra inputs and more adder cells along with extra circuitry. Using the modified summand-generator, other types of multipliers can be easily constructed to be testable with only one extra input. Test sets for these multipliers can be obtained using the same test generation approach.>