RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns
Karam S. Chatha, Ranga R. Vemuri · 1998
Hardware/Software designs of embedded systems are characterized by stringent performance constraints. Pipelined implementation of a design is an effective way for maximizing the performance of a design. In this paper we present a novel retiming heuristic to obtain pipelined schedules for hardware-software codesigns. The heuristic aims at maximizing the throughput of a loop oriented resource constrained codesign while minimizing its shared memory usage. The effectiveness of the proposed technique is demonstrated by experimentation. 1 Introduction Hardware/Software codesign process transforms a system specification into interacting hardware (HW) and software (SW) components (or tasks) which exhibit the desired behavior and satisfy the given performance constraints. A typical codesign architecture consists of a single general purpose software processor, a single application specific integrated circuit (ASIC) and a shared memory (see Figure 1), all connected through the system bus. Commu...