PAR-APLAC: Parallel Circuit Analysis and Optimization
Eila Pajarre, T. Ritoniemi, Hannu Tenhunen · European Design Automation Conference · 1992
The authors describe a circuit simulation, analysis and optimization software which can utilize the most common parallel processing hardware, i.e. the workstation network. The parallel processing ability has been implemented using an easy-to-use but powerful methodology. The efficiency of this methodology is demonstrated in terms of both CPU and programmer time. The feasibility of converting even large existing software systems for at least partial parallel execution is demonstrated. With a suitable set of tools the amount of changes which are needed is small. Despite the limited bandwidth of an Ethernet network, a set of networked computers can be used as an efficient parallel processor for some of the problems in electronic design automation. >