A closer look at multiple faults and defect levels in digital circuits
E.J. Aas · 2003
The defect level versus production yield and fault coverage of test programs for VLSI chips is investigated. The focus is on low yield, for which multiple faults are dominant. Various multiple fault coverage models are presented, and the importance of choosing an accurate model for multiple fault coverage is demonstrated. Finally, fault simulation results are presented. Single, double, and triple fault coverages are calculated and compared against the theoretical models.>